WJEC A Level Electronics ET2 — Unit Papers & Mark Schemes

Sequential logic questions test your ability to trace circuit operation over multiple clock cycles. When analysing a counter circuit, draw a timing diagram with the clock signal at the top, then add each flip-flop output below. Trace one clock edge at a time, determining the new state of each flip-flop from its inputs at the moment of the triggering edge. The 555 timer is a frequent examination topic. Memorise the formulae for astable frequency (f = 1.44 / ((R1 + 2R2) × C)) and monostable pulse duration (t = 1.1 × R × C), and practise calculating component values to achieve specified timing. Always draw the pin connections correctly: pins 2 (trigger), 3 (output), 4 (reset), 6 (threshold), 7 (discharge). Shift register questions may ask you to trace data through a series of flip-flops or to design a register for serial-to-parallel conversion. Practise both SISO (serial in, serial out) and SIPO (serial in, parallel out) configurations, noting how many clock pulses are needed to load a given data word.